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I'm FPGA design engineer, and I'm thinking in learning more about Ethereum to make a FPGA implementation, but I've read in many sites that Ethereum is ASIC resistant but I couldn't find any technical explanation.

Why is not possible to create a FPGA/ASIC implementation connected to a pool?

Can anyone bring tech details on why is impossible to create an Ethereum ASIC/FPGA miner?

Thanks in advance!

marked as duplicate by Richard Horrocks, lungj, Ismael, carver, eth Sep 8 '17 at 6:17

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By design Ethereum is ASIC resistant to avoid mining centralisation and to createa more fair currency. It implements Ethash(the pow algorithm for ethereum) which needs lot of memory unavailable for ASIC chips. So by design we don't need ASIC mining so it's a waste of effort to try building an ASIC miner.

  • I wonder how much memory is that? – Steve Kero Jan 5 '18 at 17:12

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