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I'm FPGA design engineer, and I'm thinking in learning more about Ethereum to make a FPGA implementation, but I've read in many sites that Ethereum is ASIC resistant but I couldn't find any technical explanation.
Why is not possible to create a FPGA/ASIC implementation connected to a pool?
Can anyone bring tech details on why is impossible to create an Ethereum ASIC/FPGA miner?
Thanks in advance!